The present invention relates to a high voltage switch circuit for selectively applying a high voltage to a nonvolatile memory.
FIG. 1 illustrates a prior-art high voltage switch circit. In the drawing, reference numeral 1 denotes a high voltage input terminal, numeral 2 denote an output terminal, numerals 3 and 4 denote clock input terminals, numerals 5, 6, 7, 8, 9 and 10 denote MOS transistors, and numerals 11 and 12 denotes capacitors.
The source of the first MOS transistor 5 is connected to the drain and the gate of the second MOS transistor 6, the source of the second MOS transistor 6 is connected to the gate of the first MOS transistor 5, the drain of the third MOS transistor 8 and the gate of the fourth MOS transistor 7, the input terminal 1 is connected to the drains of the first and fourth MOS transistors 5 and 7, and the output terminal 2 is connected to the sources of the third and fourth MOS transistors 8 and 7.
Numerals 9 and 10 denote MOS transistors. These transistors 9 and 10 are connected in series between a power source VDD and a ground GND, the connecting point of both the transistors is connected to the output terminal, and are turned ON or OFF by a control circuit for selectively applying a high voltage to a predetermined nonvolatile memory cell. The power source VDD voltage is applied to the gate of the MOS transistor 8, and the capacitors 11 and 12 are respectively provided between the clock input terminals 3, 4 and the gates of the MOS transistors 5, 6.
The operation of the prior-art high voltage switch circuit will be described here below. In case the transistor 9 is now ON and the transistor 10 is OFF, the gate voltage of the transistor 5 is VDD-VTH, and the source become VDD-2VTH. When a clock 4 goes from a low to high in this state, the drain voltage of the transistor 6 becomes high due to the capacitive coupling, with the result that the source voltage of the transistor 6 rises through the channel of the transistor 6. This operation is repeated, the gate voltage of the transistor 7 becomes higher than the voltage of the input terminal 1, and the voltage of the input terminal 1 is transmitted to the output terminal 2. In case the transistor 9 is OFF and the transistor 10 is ON, the gate of the transistor 6 becomes the GND voltage in OFF state, with the result that the voltage of the output terminal 2 remains GND.
Since the prior-art high voltage switch circuit is constructed as described above, in case the transistor 9 is OFF and the transistor 10 is ON, the switch circuit is in a nonactive stage, clock pulses are input from the clock input terminals 3, 4. Therefore, a low voltage is induced at the gate of the transistor 7 by the capacitive coupling, with the result that there arises a problem that the low voltage is transmitted from the input terminal 1 to the output terminal 2.